Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022
Public

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2.4.3. Specifying the Clock, Sample Depth, and RAM Type

You must specify options for the acquisition clock, sample depth, and data storage on the Signal Configuration pane before using Signal Tap.
Note: The Signal Tap file templates automatically specify appropriate initial values for some of these options.
Figure 31. Clock, Sample Depth, and Data Storage Options

Specifying the Acquisition Clock

Signal Tap samples data on each positive (rising) edge of the acquisition clock. Therefore, Signal Tap requires a clock signal from your design to control the logic analyzer data acquisition. For best data acquisition, specify a global, non-gated clock that is synchronous to the signals under test. Refer to the Timing Analysis section of the Compilation Report for the maximum frequency of the logic analyzer clock.

  • To specify the acquisition clock signal, enter a signal name from your design for the Clock setting in Single Configuration.
Note: Consider the following when specifying the acquisition clock:
  • If you do not assign an acquisition clock, Signal Tap automatically creates clock pin auto_stp_external_clk. You must then make a pin assignment to this signal, and ensure that a clock signal in your design drives the acquisition clock.
  • Using a transceiver recovered clock as the acquisition clock can cause incorrect or unexpected behavior, particularly when the transceiver recovered clock is the acquisition clock with the power-up trigger feature.
  • Specifying a gated acquisition clock can result in unexpected data that does not accurately reflect the behavior of your design.
  • Signal Tap does not support sampling on the negative (falling) clock edge.

Specifying Sample Depth

The sample depth determines the number of samples the logic analyzer captures and stores in the data buffer, for each signal. In cases with limited device memory resources, you can reduce the sample depth to reduce resource usage.

  • To specify the sample depth, select the number of samples from the Sample depth list under Single Configuration. Available sample depth range is from 0 to 128K.

Specifying the RAM Type

You can specify the RAM type and buffer acquisition mode for storage of Signal Tap logic analyzer acquisition data. When you allocate the Signal Tap logic analyzer buffer to a particular RAM block, the entire RAM block becomes a dedicated resource for the logic analyzer.

  • To specify the RAM type, select a Ram type under Single Configuration. Available settings are Auto, MLAB, or M20K RAM.

Use RAM selection to preserve a specific memory block for your design, and allocate another portion of memory for Signal Tap data acquisition. For example, if your design has an application that requires a large block of memory resources, such as a large instruction or data cache, use MLAB blocks for data acquisition and leave M20k blocks for your design.

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