ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Document Table of Contents

Timing Violation

The following figure shows a timing violation in the example design. This path is related to DQS enable control and is valid. Some calibration algorithm is required to control the DQS enable block.

Figure 45. Timing Violation

Without any calibration algorithm in place, this path cannot be set as false path in the static timing analysis.

set_false_path Command

#set_false_path -from [get_keepers {*|dqs_enable_ctrl~DQSENABLEOUT_DFF}] -to [get_clocks{dqs_out}]

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