ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Public
Document Table of Contents
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DQ and DQS Input Paths for Stratix V Devices

The following figure shows the input paths where x = 0 to (n-1) and n = the number of DQ pins.

Figure 1. DQ and DQS Input Paths for Stratix V Devices


Note:

For more information about the DQ and DQS input path with a hard read FIFO block, refer to Figure 1 and Figure 1.