ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Document Table of Contents

Altera PLL Clock Settings Information

The following table lists the clock settings Information. You can either merge the similar frequency counters in their design, or the Fitter performs the merging automatically.

Table 10.  Altera PLL Clock Settings Information
Clock Description
outclk_0 600 MHz, used as 2x frequency if necessary.
outclk_1 300 MHz, used as strobe/dqs clock.
outclk_2 300 MHz, 270 degrees phase shifted. Used as data/dq clock.
outclk_3 150 MHz, used as half-rate clock.
outclk_4 300 MHz, used to drive the ALTDLL IP core. The minimum frequency for the ALTDLL IP core for Stratix V devices is 300 MHz.
outclk_5 300 MHz, used to drive the full rate core clock.
outclk_6 150 MHz, used to drive the half rate core clock.
outclk_7 25 MHz, used as config_clk.
Note: lf the memory frequency is less than the ALTDLL IP core minimum frequency, then drive the ALTDLL IP core at 2x or 4x of the memory frequency. The DQS phase settings decrease as well.