ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

ALTDQ_DQS2 Dynamic Configuration Ports

The following table lists the dynamic configuration ports where n= number of DQ pins and m= number of additional DQ pins.

ALTDQ_DQS2 Dynamic Configuration Ports

Port name

Type

Width

Description

config_clock_in

Input

1

The ALTDQ_DQS2 dynamic configuration interface consists of this input port.

Receives the clock signal to clock all dynamic configuration blocks. You can connect this port to a clock pin, or the PLL clock output port.

This is the clock signal. All other input signals must be treated as synchronous to this clock.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

config_data

Input

1

The ALTDQ_DQS2 dynamic configuration interface consists of this input port.

The 1-bit serial input through which data is scanned into the calibration blocks. It is common to all configuration blocks, but it will only be scanned into calibrations blocks whose enable input is asserted.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

For Stratix V GX and Arria V GZ devices, the bitstream for config_data must be LSB first (from LSB to MSB).

For Arria V and Cyclone V devices, the bitstream for config_data must be MSB first (from MSB to LSB).

config_io_ena[]

Input

n

An input port that controls the enable input on the DQ I/O configurations. Receives the clock enable signal for the I/O configuration block.

Refer to Dynamic Reconfiguration for ALTDQ_DQS2

This port is supported in Arria V, Cyclone V, and Stratix V devices.

config_dqs_io_ena

Input

1

An input port that controls the enable input on the DQS I/O configurations. Receives the clock enable signal for the DQS I/O configuration block.

Refer to Dynamic Reconfiguration for ALTDQ_DQS2

This port is supported in Arria V, Cyclone V, and Stratix V devices.

config_dqs_ena

Input

1

An input port that controls the enable input on the DQS logic. Receives the clock enable signal for the DQS configuration block.

Refer to Dynamic Reconfiguration for ALTDQ_DQS2

This port is supported in Arria V, Cyclone V, and Stratix V devices.

config_update

Input

1

The ALTDQ_DQS2 dynamic configuration interface consists of this input port.

Receives the signal to load the bits from the serial-to-parallel shift registers to the configuration registers.

After scanning all the bits into the desired scan chain blocks, the bits can be copied at once into the configuration register by asserting the config_update signal for one clock cycle.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

config_data_in

Input

1

Receives the serial configuration data stream that shifts into the serial‑to-parallel shift registers.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

config_extra_io_ena[]

Input

m

Receives the clock enable signal for the additional I/O configuration block.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

Note: For more information about the dynamic configuration blocks in Stratix V device, refer to “I/O Configuration Block and DQS Configuration Block” in the External Memory Interfaces in Stratix V Devices chapter of the Stratix V Device Handbook.
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