ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Public
Document Table of Contents

ALTDQ_DQS2 Data Ports

The following table lists the ALTDQ_DQS2 data ports where n= number of DQ pins, m= number of additional output-only DQ pins, x = 0 to (n-1), and y= 0 to (m-1).
ALTDQ_DQS2 Data Ports

Port Name

Type

Width

Description

extra_write_data_in[]

Input

2m = full-rate

4m = half-rate

Receives data signal from the core.

This port connects to the input port of the half-rate data to single-rate data output registers block (Figure 2). In full-rate mode, only the extra_write_data_in[y] and extra_write_data_in[m+y] ports are used.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

extra_write_data_out[]

Output

m

Sends data to the external device.

This port connects to the output port of the output buffer (Figure 2).

This port is supported in Arria V, Cyclone V, and Stratix V devices.

read_data_in[]

Input

n

Receives data from the external device.

This port connects to the input port of the input buffer located between the DQ pin and the DDR input registers block. This is an input-only DQ port that receives data from the external device (Figure 1).

This port is supported in Arria V, Cyclone V, and Stratix V devices.

read_data_out[]

Output

2n = full-rate

4n = half‑rate

Sends the captured data from the external device to the core.

This port connects to the output port of the DDR input register block (Figure 1). The read_data_out[x] port outputs the positive-edge triggered data, and the read_data_out[n+x] port outputs the negative-edge triggered data.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

read_write_data_io[]

Bidirectional

n

Receives and sends data between the core and the external device.

You must assign the bidirectional DQ port with the output termination and input termination assignments.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

write_data_in[]

Input

2n = full-rate

4n = half-rate

Receives DDR data signal from the core to be sent out to the external device. For example, data to be written to the external memory during write operation.

This port connects to the input port of the half-rate data to single-rate data output registers block (Figure 1). In full-rate mode, the IP core uses only the write_data_in[x] and write_data_in[n+x] ports.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

write_data_out[]

Output

n

Sends the DDR data signal to the external device. For example, data to be written to the external memory during write operation.

This port connects to the output port of the output buffer located between the DDR output registers block and the DQ‑out pin (Figure 1).

This port is supported in Arria V, Cyclone V, and Stratix V devices.

write_oe_in[]

Input

n = full-rate

2n = half-rate

Receives the gating signal from the core to control the output buffer. For example, gating control when writing data to the external memory during write operation.

This port connects to the input port of the half-rate data to single-rate data output-enable registers block (Figure 1). In full-rate mode, the IP core uses only the write_oe_in[x] port.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

Note: To understand how these ports connect to the IOEs, refer to “I/O Elements” in the External Memory Interfaces in Stratix V Devices chapter of the Stratix V Device Handbook.
The port width applies to full-rate mode, unless otherwise specified.

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