ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Public
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ALTDQ_DQS2 Data Strobe Ports

ALTDQ_DQS2 Data Strobe Ports

Port Name

Type

Width

Description

capture_strobe_ena

Input

1

Controls the DQS enable control block by acting as the gating signal for signals coming from the input registers (capture_strobe_in) to reach the DQS delay chain block.

This port is only supported in Stratix V devices.

capture_strobe_n_in

Input

1

Receives the negative polarity clock signal from the external device. For example, a DQSn signal from the external memory. This port is available when the capture strobe type is set to differential or complementary.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

capture_strobe_in

Input

1

Receives the clock signal from the external device, for example, a DQS signal from the external memory.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

capture_strobe_out

Output

1

Sends the delayed clock signal to the core. For example, a delayed DQS signal from the DQS delay chain.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

output_strobe_ena

Input

2 = half-rate

1 = full-rate

The gating signal for the output_strobe_out port.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

oct_ena_in

Input

2 = half-rate

1 = full-rate

Controls the dynamic on-chip-termination signal for all data and strobe ports.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

reset_n_core_clock_in

Input

1

Asynchronous reset used in QDRII-like interfaces to reset the write strobe.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

write_strobe_clock_in

Input

1

Receives the clock signal from the core. For example, a DQS signal from the core. Clocks the DDIO that generates the output strobe signal.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

Note: This signal is the main full-rate input clock when you set the IP type to Input for Arria V and Cyclone V devices.
strobe_ena_hr_clock_in

Input

1

Receives the clock signal from the clock pin or the PLL to clock the DQS enable control block.

Also a half-rate signal that, after going through the DQS_ENABLE_CTRL input, controls the gating of the input strobe.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

strobe_io

Bidirectional

1

Sends and receives the bidirectional clock signal.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

strobe_n_io

Bidirectional

1

Sends and receives the negative polarity clock signal for differential or complementary strobe configuration.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

output_strobe_out

Output

1

Sends clock signal to the external device. For example, a DQS signal to the external memory.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

output_strobe_n_out

Output

1

Sends the negative polarity clock signal to the external device (For example, DQSn signal to the external memory). This port is available when you set the output strobe type to differential or complementary.

This port is supported in Arria V, Cyclone V, and Stratix V devices.