ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Document Table of Contents
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FIFO Control

For Arria V and Cyclone V devices, in addition to the read FIFO and the data valid FIFO, the location of the latency shifter FIFO is in each DQS group. The latency shifter FIFO takes in a read‑enable command from the core and implements a programmable latency of up to 32 cycles before feeding into the read-enable port of the read FIFO.

You can use the output of the data valid FIFO to perform the following tasks:

  • To ungate the DQS logic when a strobe signal is capturing the data. In this case, the write-enable port must always be '1' on the read FIFO.
  • To enable the read FIFO write-enable port when a clock is in use.

The following figure shows the three FIFOs interconnection.

Figure 3. Data Valid FIFO, Latency Shifter FIFO, and Read FIFO Interconnection

When a read command is sent to the memory device, a read-data-enable token is pushed through the data valid FIFO and the latency shifter FIFO. The data valid FIFO implements a latency equal to the read command to data latency. When the token comes out of the data valid FIFO, the DQS signal is ungated. The latency shifter FIFO then creates enough space between write and read pointers in the read FIFO to ensure that the data read on the read side is correct. If the read FIFO is read at half-rate, the read FIFO also implements a full-rate to half-rate conversion.

The determination of the correct latencies to implement at each of these FIFOs is important and cannot be done during compilation. When you attempt to implement your own custom memory solution, you must also implement some form of calibration algorithm.

To determine if the data coming from the read FIFO is valid, you must implement the read data valid latency in soft logic.