ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Document Table of Contents

ALTDQ_DQS2 Features

The ALTDQ_DQS2 IP core has the following features:

  • Access to dynamic on-chip termination (OCT) controls to switch between parallel termination during reads and series termination during writes.
  • High-performance support for DDR interface standards.
  • 4- to 36-bit programmable DQ group widths.
  • Half-rate registers to enable successful data transfers between the I/O registers and the core logic.
  • Access to I/O delay chains to fine-tune delays on the data or strobe signals.
  • Access to hard read FIFO.
  • Access to latency shifter FIFO and data valid FIFO for efficient control of DQS gating and read operations (Arria V and Cyclone V devices only).