ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Document Table of Contents

Setting Up NativeLink and Simulation Settings

To set up the NativeLink and simulation settings, follow these steps:

  1. In the Quartus® Prime software, on the Tools menu, select Options.
  2. In the Options dialog box, under Category list, expand General and then select EDA Tool Options.
  3. In the EDA Tools Options window, follow the settings as shown in the following figure:
    Figure 31. EDA Tools Options Dialog Box

  4. In the Quartus® Prime software, on the Assignments menu, click Settings.
  5. In the Settings dialog box, under the Category list, expand EDA Tool Settings. Click Simulation.
  6. Enter the necessary NativeLink settings. The following figure shows an example settings. In this design example, a testbench (tb.v) is provided together with other supporting files.
    Figure 32. Simulation Dialog Box

    Figure 33. Test Benches Dialog Box

    Figure 34. Edit Test Bench Settings Dialog Box

  7. Run Analysis and Synthesis.
  8. To view the simulation results, on the Tools menu, select Run Simulation Tool and then click RTL Simulation.
    For a successful simulation, you may need to manually change alterapll.v to alterapll.vo in the auto-generated file.
  9. Before running the Fitter, ensure that the following settings are done in the Assignment Editor.
    • I/O Standard
    • Input Termination
    • Output Termination
    • DQ Group
    • Location assignment for strobe pin—this helps the Fitter to fit the related DQ pins in the appropriate l/O sub-banks. You can then back-annotate the locations if desired.
    The following figure shows an example setting in the Assignment Editor and the Pin Planner results:
    Figure 35. Assignment Editor Window

    Figure 36. Pin Planner

  10. Run the Fitter, Timing Analysis, and Assembler. An SDC example (top.sdc) is included in the example design.
    Arria V device uses the PHYCLK by default.
    Figure 37. Design Example Clock Routing in Arria V Device