ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Public
Document Table of Contents
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Blocks in DQ and DQS Output Path

The following table lists the blocks in the DQ and DQS output path.

Blocks in the DQ and DQS Output Path
Block Name Description

Half-rate to single-rate output enable registers

Represents a group of registers that convert half-rate data to single-rate data.

Output phase alignment registers

Represents the circuitry required to phase shift the DQ-output signals. Use this block for write‑leveling purposes in DDR3 SDRAM interfaces.

DDR output registers

Represents the DDIO registers that transfer DDR signals from the core to the DQ/DQS pins.