ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Document Table of Contents

SDC Walkthrough

To create a new .sdc, follow these steps:

  1. Constrain the clocks coming into the FPGA with a create_clock command. The following command creates the base clock for the input clock port driving the PLL:
    create_clock -name refclk -period 10.000 [get_ports {refclk}]
  2. Create the generated clocks for the PLL with the following command:
  3. Apply inter-clock, intra-clock and I/O interface uncertainties based on timing model characterization using the following command:
  4. Constraint the virtual input clock (for incoming DQS strobe) and the capture_strobe_in port. ln this example design, it is based on a 250 MHz input clock, with a 50% duty cycle, where the first rising edge occurs at 0 ns.

    create_clock -name virtual_dqs_in -period 4.000 -waveform {0 2.000}

    create_clock -name dqs_in -period 4.000 -waveform {0 2.000}[get_ports {capture_strobe_in}]