ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Document Table of Contents

DQS Logic

The DQS input path in Arria V and Cyclone V devices has the following differences from Stratix V and earlier versions of the device families:

  • A data valid FIFO delays the DQS enable path by up to 16 full-rate cycles. During a required calibration process, you can increase the unknown delay, which the data valid FIFO implements, by 1, by pulsing the INC_WR_PTR port. The delay wraps around after 16 increments.
  • The DQS delay chain implements a static non-programmable phase shift of 90°.

The following figure shows the DQS input path in Arria V and Cyclone V devices.

Figure 2. DQS Input Path in Arria V and Cyclone V Devices