ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Document Table of Contents

DQS Read Operation

Between 19.227 ms and 19.275 ms when the dqs_readdata_valid signal is held high, data validation is done by comparing data received by the ALTDQ_DQS2 core (read_data_out) against the content in the check_fifo.

ln Stratix V devices, you can choose to enable or disable the hard read FlFO. The read FlFO is in every input data paths. The read FlFO handles full-rate and half-rate conversion only. This example design uses the hard read FlFO. The testbench determines the timing to assert the write enable and read enable ports via the v/i/o_qvld and l/i/o_rden. ln an actual application, you must design your own logic to do so.

The DQS driver begins the DQS read operation when the dqs_read signal is asserted at 19.139 ms, for the entire length of the desired read burst, which in this case is 12 full-rate cycles. The DQS agent also receive the read command, and is ready to send out data. After a specific latency, the agent_output_enable signal is asserted beginning from 19.167 ms to 19.219 ms. During this period, the DQS agent drives clock and data lines of the external memory interface. The oct_enable signal is asserted between 19.155 ms and 19.211 ms. The incoming data (dq) is edge-aligned to the clock (dqs_agent_to_ios).

DQS Read Operation Waveform