Parallel Flash Loader Intel® FPGA IP User Guide

ID 683698
Date 7/23/2021
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Document Table of Contents

1. Parallel Flash Loader Intel® FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.1
IP Version 19.1.0
This document describes how to instantiate the Parallel Flash Loader (PFL) Intel® FPGA IP core in your design, programming flash memory, and configuring your FPGA from the flash memory.

FPGAs’ increasing density requires larger configuration storage. If your system contains a flash memory device, you can use your flash memory as the FPGA configuration storage as well. You can use the PFL IP core in Intel® MAX®  devices ( Intel® MAX® 10, MAX® II, and MAX® V devices) or all other FPGAs to program flash memory devices efficiently through the JTAG interface and to control configuration from the flash memory device to the Intel® FPGA.

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