Parallel Flash Loader Intel® FPGA IP User Guide

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ID 683698
Date 7/23/2021
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Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.4.2.4. Summary of PFL Timing Constraints

Table 8.  PFL Timing Constraints
Type Port Constraint Type Delay Value
Input clock pfl_clk create_clock Can be constrained up to the maximum frequency supported by the PFL IP core.
Input asynchronous pfl_nreset set_false_path —
fpga_pgm set_false_path —
fpga_conf_done set_false_path —
fpga_nstatus set_false_path —
pfl_flash_access_granted set_false_path —
pfl_nreconfigure set_false_path —
Output asynchronous fpga_nconfig set_false_path —
pfl_flash_access_request set_false_path —
flash_nce set_max_delay -from pfl_clk -to <port> Determined by

Taccess/Tpage_access

and board delay
flash_nwe set_false_path —
flash_noe set_false_path —
flash_addr set_max_delay -from pfl_clk -to <port> Determined by

Taccess/Tpage_access

and board delay
Bidirectional synchronous flash_data
  • Read mode (Flash ROM to PFL)

    set_max_delay -from <port> to pfl_clk

  • Write mode (PFL to Flash ROM) set_false_path
Read mode:

Determined by

Taccess/Tpage_access and board delay
Output synchronous fpga_data set_output_delay -clock fpga_dclk <port> Determined by board delay and TSU/TDH of the FPGA
Output Clock fpga_dclk
  • Input clock to DCLK ratio = 1 create_generated_clock -source pfl_clk -invert <fpga_dclk port>

  • Input clock to DCLK ratio >1 create_generated_clock -source pfl_clk -divide_by <ratio> <*fpga_dclk_reg at register>

    create_generated_clock -source <*fpga_dclk_reg at register> <fpga_dclk at port>
Input clock to DCLK ratio >1:
Set muticycle path using launch clock
  • Setup relationship by half of ratio
  • Hold relationship by ratio -1
Level Two Title