220.127.116.11. Programming CFI Flash
The Intel® CPLD JTAG block interfaces directly with the logic array in a special JTAG mode. This mode brings the JTAG chain through the logic array instead of the Intel® CPLD boundary-scan cells (BSCs). The PFL IP core provides JTAG interface logic to convert the JTAG stream provided by the Intel® Quartus® Prime software and to program the CFI flash memory devices connected to the CPLD I/O pins.
The PFL IP core supports dual MT28EW CFI flash memory devices in burst read mode to achieve faster configuration time. Two identical MT28EW CFI flash memory devices connect to the CPLD in parallel using the same data bus, clock, and control signals. During FPGA configuration, the FPGA DCLK frequency is four times faster than the flash_clk frequency.
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