Parallel Flash Loader Intel® FPGA IP User Guide

ID 683698
Date 7/23/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Programming CFI Flash

Intel® configuration devices support programming through the JTAG interface to allow in-system programming and updates. However, standard flash memory devices do not support the JTAG interface. You can use the JTAG interface in Intel® CPLDs to indirectly program the flash memory device.

The Intel® CPLD JTAG block interfaces directly with the logic array in a special JTAG mode. This mode brings the JTAG chain through the logic array instead of the Intel® CPLD boundary-scan cells (BSCs). The PFL IP core provides JTAG interface logic to convert the JTAG stream provided by the Intel® Quartus® Prime software and to program the CFI flash memory devices connected to the CPLD I/O pins.

Figure 2. Programming the CFI Flash Memory with the JTAG InterfaceFigure shows an Intel® CPLD configured as a bridge to program the CFI flash memory device through the JTAG interface.

The PFL IP core supports dual MT28EW CFI flash memory devices in burst read mode to achieve faster configuration time. Two identical MT28EW CFI flash memory devices connect to the CPLD in parallel using the same data bus, clock, and control signals. During FPGA configuration, the FPGA DCLK frequency is four times faster than the flash_clk frequency.

Note: Dual mode is also supported in P30 and P33 devices.
Figure 3. PFL IP core with Dual MT28EW CFI Flash Memory DevicesThe flash memory devices in the dual MT28EW CFI flash solution must have the same memory density from the same device family and manufacturer.

Did you find the information on this page useful?

Characters remaining:

Feedback Message