You can also use the JTAG interface in Intel® CPLDs to program a quad SPI flash memory device with the PFL IP core.
The PFL IP core instantiated in the Intel® CPLD functions as a bridge between the CPLD JTAG programming interface and the quad SPI flash memory device interface that connects to the Intel® CPLD I/O pins. You can connect up to eight identical quad SPI flashes in parallel to implement more configuration data storage.
Note: When connecting quad SPI flashes in parallel, use identical flash memory devices with the same memory density from the same device family and manufacturer.
Figure 4. Programming Quad SPI Flash Memory Devices With the CPLD JTAG InterfaceFigure shows an Intel® CPLD functioning as a bridge to program the quad SPI flash memory device through the JTAG interface. The PFL IP core supports multiple quad SPI flash programming of up to four devices.
Note: The PFL IP core supports multiple quad SPI flash programming of up to eight devices.