Parallel Flash Loader Intel® FPGA IP User Guide

ID 683698
Date 7/23/2021

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1.3.5. Using Enhanced Bitstream Compression and Decompression

The enhanced bitstream compression and decompression feature in the PFL IP core reduces the size of the configuration file in the flash memory device. On average, you can reduce the file size by as much as 50% depending on the designs. When you turn on the enhanced bitstream compression feature, the PFL IP core disables data encryption.
Table 6.  Comparison Between Typical, Enhanced, and Double Compression
FPGA Configuration Typical Bitstream Compression Feature Enhanced Bitstream Compression Feature Double Compression Technique
FPGA on-chip bitstream decompression enabled Yes No Yes
PFL enhanced bitstream decompression enabled No Yes Yes
Typical configuration file size reduction 35%–55% 45%–75% 40%–60%
PS configuration time Moderate 12 Slow Moderate12
FPP configuration time Fast13 Very fast14 Not supported
Note: When using the PFL with compression, set the device MSEL pins set for compression or decompression. When generating or converting a programming file, you can enable compression. In the first few bytes during the generation of the programming file (with compression enabled), a bit set notifies the PFL that the incoming files is a compressed file. The ×4 DCLK-to-data are handled automatically in the PFL.
Note: For more information about the typical data compression feature, refer to the Configuration Data Decompression section in the configuration chapter of the relevant device handbook.

For the FPP configuration scheme, the enhanced bitstream compression feature helps achieve higher configuration data compression ratio and faster configuration time. For the PS configuration scheme, the double compression technique helps achieve higher configuration data compression ratio and moderate configuration time. To enable the double compression technique, turn on both the typical bitstream compression feature and the enhanced bitstream compression feature in the PFL parameter editor.

Figure 13. FPGA Configuration Data Flow with Enhanced Bitstream Compression Feature in PS or FPP Configuration Scheme
Figure 14. FPGA Configuration Data Flow with Double Compression Technique in PS Configuration Scheme
12 The FPGA receives compressed bitstream which decreases the duration to transmit the bitstream to the FPGA.
13 For FPP with on-chip bitstream decompression enabled, the DCLK frequency is ×2, ×4, or ×8 the data rate, depending on the device. You can check the relationship of the DCLK and data rate in the FPP Configuration section in the configuration chapter of the respective device handbook.
14 For FPP with enhanced bitstream decompression enabled, the DCLK frequency is ×1 the data rate.