Parallel Flash Loader Intel® FPGA IP User Guide

ID 683698
Date 7/23/2021

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Document Table of Contents

1.2.2. Supported Schemes and Features

The PFL IP core allows you to configure the FPGA in passive serial (PS) or fast passive parallel (FPP) scheme. The PFL IP core supports configuration with FPGA on-chip data compression and data encryption.

When you use compressed or encrypted configuration data for FPP configuration, the PFL IP core holds one data byte for one, two, four, or eight DCLK cycles to ensure the DCLK frequency runs at the required data rate as specified by the DCLK-to-DATA[] Ratio. The PFL IP core checks if the compression or encryption feature is turned on in the configuration image before configuring in FPP mode. Hence, no additional setting is required in the PFL IP core to specify whether the configuration file stored in the flash memory device is a compressed or uncompressed image.

Note: When you turn on the enhanced bitstream compression feature, data encryption is disabled.

You can program the Intel® CPLDs and flash memory device in Programmer Object File (.pof), Jam™ Standard Test and Programming Language (STAPL) Format File (.jam), or JAM Byte Code File (.jbc) file format. The PFL IP core does not support Raw Binary File (.rbf) format.

Logic element (LE) usage varies with different PFL IP core and software settings. To determine the exact LE usage number, compile a PFL design with your settings using the software.