1.3.2. Controlling Intel® FPGA Configuration from Flash Memory
You can use the PFL IP core to either program the flash memory devices, configure your FPGA, or both; however, to perform both functions, create separate PFL functions if any of the following conditions apply to your design:
- You want to use fewer LEs.
- You modify the flash data infrequently.
- You have JTAG or In-System Programming (ISP) access to the Intel® CPLD.
- You want to program the flash memory device with non- Intel® FPGA data. For example, the flash memory device contains initialization storage for an ASSP. You can use the PFL IP core to program the flash memory device with the initialization data and also create your own design source code to implement the read and initialization control with the CPLD logic.
Creating Separate PFL Functions
To create separate PFL functions, follow these steps:
- To create a PFL instantiation, select Flash Programming Only mode.
- Assign the pins appropriately.
- Compile and generate a .pof for the flash memory device. Ensure that you tri-state all unused I/O pins.
- To create another PFL instantiation, select Configuration Control Only mode.
- Instantiate this configuration controller into your production design.
- Whenever you must program the flash memory device, program the CPLD with the flash memory device .pof and update the flash memory device contents.
- Reprogram the CPLD with the production design .pof that includes the configuration controller.
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