18.104.22.168. Implementing Remote System Upgrade with the PFL IP Core
To control the fpga_pgm[2..0] and the pfl_nreconfigure ports, user-defined logic must perform the following capabilities:
- After FPGA power-up, user logic sets the fpga_pgm[2..0] ports to specify which page of configuration image is to be loaded from the flash.
- After the remote host completes the new image update to the flash, user logic triggers a reconfiguration by pulling the pfl_nreconfigure pin low and setting the fpga_pgm[2..0] to the page in which the new image is located. The pfl_nreconfigure signal pulsed low for greater than one pfl_clk cycle.
- If you have enabled the user watchdog timer, user logic can monitor the pfl_watchdog_error port to detect any occurrence of watchdog time-out error. If the pfl_watchdog_error pin is asserted high, this indicates watchdog time-out error. You can use the user logic to set the fpga_pgm[2..0] and pull the pfl_nreconfigure port low to initiate FPGA reconfiguration. The recovery page to be loaded from the flash memory device after watchdog timer error depends on the fpga_pgm[2..0] setting.
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