Parallel Flash Loader Intel® FPGA IP User Guide

ID 683698
Date 7/23/2021

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1.4.2. Constraining PFL Timing

The PFL IP core supports the Intel® Quartus® Prime Timing Analyzer for accurate timing analysis on the Intel® IP cores. To perform timing analysis, you must define the clock characteristics, external path delays, and timing exceptions for the PFL input and output ports. This section provides guidelines for defining this information for PFL input and output ports for use by the Timing Analyzer.
Note: The Timing Analyzer is a timing analysis tool that validates the timing performance of the logic in the design using industry-standard constraint, analysis, and reporting methodology. For more information about the Timing Analyzer, refer to the Intel® Quartus® Prime Timing Analyzer chapter in volume 3 of the Intel® Quartus® Prime Handbook.
Note: After you specify the timing constraint settings for the clock signal and for the asynchronous and synchronous input and output ports in the Timing Analyzer, on the Constraints menu, click Write SDC File to write all the constraints to a specific System Design Constraints File (.sdc). After the .sdc is written, run full compilation for the PFL design.

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