1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.6. Programming Multiple Flash Memory Devices
The PFL IP core supports multiple-flash programming of as many as 16 flash memory devices. This feature allows the PFL IP core to connect to multiple flash memory devices to perform flash programming sequentially. PFL multiple-flash programming supports both speed and area mode flash programming. For FPGA configuration, use the content in the flash memory device that connects to the nCE pin as configuration data.
To use the multiple flash programming feature, follow these steps:
- Select the number of flash memory devices connected to the CPLD in the PFL IP core parameter editor.
- Connect the nCE pins of the PFL to the nCE pins of the flash memory device in the block diagram. Compile the design.
- Click Auto Detect in the Intel® Quartus® Prime programmer. The CPLD appears as the main item, followed by a list of CFI flash memory devices detected as secondary items in the device tree.
- Attach the flash memory device .pof to each flash memory device.
- Check the boxes in the Intel® Quartus® Prime Programmer for the necessary operation and click Start.
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