1.5. PFL IP Core In Embedded Systems
The following figure shows how you can use the PFL IP core to program the flash memory device and to configure the FPGA with a Nios II processor. The configured Nios II processor uses the non-configuration data stored in the same flash memory device.
You must configure the Intel® FPGA with the Nios II processor when you power-up the board. You can store the Nios II processor image in the flash memory device and use the PFL IP core to configure the image to the Intel® FPGA. If you store the Nios II processor image in the same flash memory device you intend to program, do not overwrite the Nios II processor image when you program the flash memory device with other user data.
If you do not want to store the image in the flash memory device, you can store the Nios II image in a different storage device, for example an enhanced configuration (EPC) device or an erasable programmable configurable serial (EPCS) memory.
In Relationship Between the Four Sections in the Design Example figure above, the Nios II processor and the PFL IP core share the same bus line to the flash memory device. However, to avoid data contention, the processor and the IP core cannot access or program the flash memory device at the same time. To ensure that only one controller (the processor or the IP core), is accessing the flash memory device at any given time, you must tri-state all output pins from one controller to the flash memory device, while the other controller is accessing the flash memory device using the pfl_flash_access_request and pfl_flash_access_granted pins in the PFL IP core.
|pfl_flash_access_request||The PFL IP core drives this pin high to request access to the flash memory device.|
|pfl_flash_access_granted||The PFL IP core enables the access to the flash memory device whenever the PFL IP core receives a high input signal at this pin.|
|Signal||Nios II Processor||PFL IP Core|
|High output signal at pfl_flash_access_request||Tri-state all output pins to the flash memory device.||Connect all input and output pins to the flash memory device when the pfl_flash_access_granted pin receives a high input.|
|Low output signal at pfl_flash_access_request||Reconnect all pins to the flash memory device.||Tri-state all output pins to the flash memory device when the pfl_flash_access_granted pin receives a low input.|
The Intel® CPLD and Nios II processor can each program the CFI flash memory device individually. To prevent both processors from accessing the CFI flash memory device at the same time, the flash_access_granted and flash_access_request pins of the CPLD and Nios II processor are connected together.
To use other processors or controllers in place of the Nios II processor, ensure that the pfl_flash_access_granted and pfl_flash_access_request pins of the PFL IP core connect to your processor using the method in pfl_flash_access_request and pfl_flash_access_granted Pins With the Nios II and PFL IP Core table above.
You must also specify the flash memory device read or write access time for your processor or controller. To avoid data contention when the PFL IP core is accessing the flash memory device, ensure that the output pins from your processor are tri-stated when the pfl_flash_access_request signal is high.