126.96.36.199. Remote System Upgrade State Machine in the PFL IP Core
If an error occurs while loading the configuration image, the PFL IP core triggers a reconfiguration to automatically load the factory image. After the FPGA successfully loads the configuration image, the FPGA enters user mode. After the FPGA enters user mode, you can initiate a reconfiguration to a new page by following these steps:
- Set the fpga_pgm[2.0] input pin.
- Release the pfl_nreset to high if the pfl_nreset is asserted to low.
- After fifteen clock cycles, pulse the pfl_nreconfigure input pin to low.
- Ensure that all transition is synchronized to pfl_clk.
- The remote system upgrade feature in the PFL IP core does not restrict the factory image to page 0, but allows the factory image to be located on other pages in the flash.
- You can load the FPGA with either a factory image or any application image after power up, depending on the fpga_pgm[2..0] setting.
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