Parallel Flash Loader Intel® FPGA IP User Guide

ID 683698
Date 7/23/2021

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Document Table of Contents Creating a Test Bench File for PFL Simulation

You can use a test bench file to establish the interface between the PFL IP core and the flash memory device. You must map the input and output ports of the PFL IP core to the appropriate data or address bus, and to the control signals of the flash.

To perform the signal mapping, you must include the PFL primitive block and the flash primitive block in the test bench. The primitive blocks contain the input and output ports of the device. You can obtain the flash primitive blocks from the simulation model files provided by the flash memory device manufacturer.

To establish the connection between the PFL IP core and the flash memory device, you must connect the flash data bus, the flash address bus, and the flash control signals from the PFL primitive block to the appropriate ports of the flash primitive block.

PFL Primitive Block

pfl pfl_inst (
           .fpga_pgm(<fpga_pgm source>),
           .pfl_clk(<pfl clock source>),
           .pfl_flash_access_granted(<pfl_flash_access_granted source>),
           .pfl_flash_access_request(<pfl_flash_access_granted destination>),
           .pfl_nreconfigure(<pfl_nreconfigure source>),
           .pfl_nreset(<pfl_nreset source>),
           .flash_addr(<flash address bus destination>),
           .flash_data(<flash_data bus destination>),
           .flash_nce(<flash_nce destination>),
           .flash_noe(<flash_noe destination>),
           .flash_nreset(<flash_nreset destination>),
           .flash_nwe(<flash_nwe destination>),
           .fpga_conf_done(<fpga_conf_done source>),
           .fpga_nstatus(<fpga_nstatus source>),
           .fpga_data(<fpga_data destination>),
           .fpga_dclk(<fpga_dclk destination>),
           .fpga_nconfig(<fpga_nconfig destination>),
Note: For more information about the flash simulation model files, contact the flash memory device manufacturer.

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