Visible to Intel only — GUID: yhe1594776209750
Ixiasoft
Visible to Intel only — GUID: yhe1594776209750
Ixiasoft
5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide
Date | Intel® Quartus® Prime Version | IP Version | Changes |
---|---|---|---|
2022.04.29 | 22.1 | 21.4.0 [H-Tile] 3.0.0 [P-Tile] 2.0.0 [F-Tile] |
Sections Updated:
|
2022.02.06 | 21.4 | H-Tile IP version: 21.3.0 P-Tile IP version: 2.2.0 F-Tile IP version: 1.1.0 |
|
2021.12.01 | 21.3 | H-Tile IP version: 21.2.0 P-Tile IP version: 2.1.0 F-Tile IP version: 1.0.0 |
Rev H-Tile 21.2.0—2K channel support for D2H Rev P-Tile 2.1.0—CS address width reduced from 29 to 14 bits
Rev F-Tile 1.0.0:
Added new design example: Traffic Generator/Tracker |
2021.09.15 | 21.2 | H-Tile: 21.1.0 P-Tile: 2.0.0 |
|
2021.05.24 | 21.1 | H-tile: 2.0.0 P-tile: 1.0.0 |
|
2020.08.05 | 20.2 | H-tile: 20.0.0 |
Initial Release |
Did you find the information on this page useful?
Feedback Message
Characters remaining: