Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/29/2022
Public
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Document Table of Contents
Document Table of Contents
1. Introduction 2. Design Example Detailed Description 3. Design Example Quick Start Guide 4. User Guide Archives 5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide
1. Introduction
1.1. Terms and Acronyms 1.2. MCDMA IP Modes
2. Design Example Detailed Description
2.1. Design Example Overview 2.2. Hardware and Software Requirements 2.3. PIO Using MCDMA Bypass Mode 2.4. Avalon-ST Packet Generate/Check 2.5. Avalon-ST Device-side Packet Loopback 2.6. Avalon-MM DMA 2.7. BAM_BAS Traffic Generator and Checker 2.8. External Descriptor Controller
2.1. Design Example Overview
2.1.1. MCDMA H-Tile Design Examples for Endpoint 2.1.2. MCDMA P-Tile Design Examples for Endpoint 2.1.3. MCDMA F-Tile Design Examples for Endpoint
2.3. PIO Using MCDMA Bypass Mode
2.3.1. Avalon-ST PIO Using MCDMA Bypass Mode 2.3.2. Avalon-MM PIO Using MCDMA Bypass mode
2.3.1. Avalon-ST PIO Using MCDMA Bypass Mode
2.3.1.1. Four-Port Avalon-ST PIO Using MCDMA Bypass Mode 2.3.1.2. Single-Port Avalon-ST PIO Using MCDMA Bypass Mode
2.3.1.1. Four-Port Avalon-ST PIO Using MCDMA Bypass Mode
2.3.1.1.1. Simulation Result 2.3.1.1.2. Hardware Test Result
2.3.2. Avalon-MM PIO Using MCDMA Bypass mode
2.3.2.1. Simulation Results 2.3.2.2. Hardware Test Results
2.4. Avalon-ST Packet Generate/Check
2.4.1. Four-Port Avalon-ST Packet Generate/Check 2.4.2. Single-Port Avalon-ST Packet Generate/Check
2.4.1. Four-Port Avalon-ST Packet Generate/Check
2.4.1.1. Simulation Results 2.4.1.2. Hardware Test Results
2.4.2. Single-Port Avalon-ST Packet Generate/Check
2.4.2.1. Simulation Waveforms 2.4.2.2. Simulation Log
2.5. Avalon-ST Device-side Packet Loopback
2.5.1. Simulation Results 2.5.2. Hardware Test Results
2.6. Avalon-MM DMA
2.6.1. Simulation Results 2.6.2. Hardware Test Results
2.7. BAM_BAS Traffic Generator and Checker
2.7.1. BAM_BAS Traffic Generator and Checker Example Design Register Map
2.8. External Descriptor Controller
2.8.1. Registers 2.8.2. Hardware Test Results
2.8.1. Registers
2.8.1.1. GCSR Registers (Base address 64’h00000) 2.8.1.2. QCSR Registers(Base address 64’h10000)
3. Design Example Quick Start Guide
3.1. Design Example Directory Structure 3.2. Generating the Example Design using Intel® Quartus® Prime 3.3. Simulating the Design Example 3.4. Compiling the Example Design in Intel® Quartus® Prime 3.5. Running the Design Example Application on a Hardware Setup
3.2. Generating the Example Design using Intel® Quartus® Prime
3.2.1. Procedure
3.3. Simulating the Design Example
3.3.1. Testbench Overview 3.3.2. Supported Simulators 3.3.3. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example 3.3.4. Run the Simulation Script 3.3.5. View the Results
3.5. Running the Design Example Application on a Hardware Setup
3.5.1. Program the FPGA 3.5.2. Quick Start Guide
3.5.2. Quick Start Guide
3.5.2.1. Software Test Setup 3.5.2.2. Driver Support 3.5.2.3. MCDMA Custom Driver 3.5.2.4. MCDMA DPDK Poll Mode Driver 3.5.2.5. MCDMA Kernel Mode Character Device Driver 3.5.2.6. MCDMA Kernel Mode Network Device Driver
3.5.2.3. MCDMA Custom Driver
3.5.2.3.1. Prerequisites 3.5.2.3.2. Software Setup 3.5.2.3.3. Run the Reference Example Application 3.5.2.3.4. Testing Bitstream Configuration beyond 256 Channels 3.5.2.3.5. External Descriptor Mode Verification
3.5.2.4. MCDMA DPDK Poll Mode Driver
3.5.2.4.1. Prerequisites 3.5.2.4.2. Install PMD and Test Application 3.5.2.4.3. Run the Reference Example Application
3.5.2.5. MCDMA Kernel Mode Character Device Driver
3.5.2.5.1. Prerequisites 3.5.2.5.2. Software Setup 3.5.2.5.3. Examples
3.5.2.6. MCDMA Kernel Mode Network Device Driver
3.5.2.6.1. Build and Install Netdev Driver 3.5.2.6.2. Enable VFs if SRIOV is Supported 3.5.2.6.3. Configure the Number of Channels Supported on the Device 3.5.2.6.4. Configure the MTU Value 3.5.2.6.5. Configure the Device Communication 3.5.2.6.6. Configure Transmit Queue Selection Mechanism 3.5.2.6.7. Test Procedure by Using Name Space Environment 3.5.2.6.8. PIO Test
1. Introduction
2. Design Example Detailed Description
3. Design Example Quick Start Guide
4. User Guide Archives
5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide

5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide

Date Intel® Quartus® Prime Version IP Version Changes
2022.04.29 22.1

21.4.0 [H-Tile]

3.0.0 [P-Tile]

2.0.0 [F-Tile]
Sections Updated:
2022.02.06 21.4

H-Tile IP version: 21.3.0

P-Tile IP version: 2.2.0

F-Tile IP version: 1.1.0
  • Added new design example: External Descriptor Controller
  • Added information for the Traffic Generator/Checker example design in Supported Simulators
2021.12.01 21.3

H-Tile IP version: 21.2.0

P-Tile IP version: 2.1.0

F-Tile IP version: 1.0.0

Rev H-Tile 21.2.0—2K channel support for D2H

Rev P-Tile 2.1.0—CS address width reduced from 29 to 14 bits

Rev F-Tile 1.0.0:
  • F-Tile support added
  • BAS EP design example added

Added new design example: Traffic Generator/Tracker

2021.09.15 21.2

H-Tile: 21.1.0

P-Tile: 2.0.0
  • Added SRIOV support for DPDK PMD
  • Added support for kernel mode driver
  • Added the Multi Channel DMA for FPGA IP Design Example User Guide Archives section
2021.05.24 21.1

H-tile: 2.0.0

P-tile: 1.0.0
  • Added the single-port Avalon-ST design example
  • Added support for new BAM, BAS, BAM+BAS, and BAM+MCDMA user modes
  • Added support for the DPDK PMD driver
  • Added support for the Xcelium simulator
2020.08.05 20.2

H-tile: 20.0.0

 Initial Release
Level Two Title

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