Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/29/2022
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2.3.1.1. Four-Port Avalon-ST PIO Using MCDMA Bypass Mode

Figure 1. Four-port Avalon-ST PIO Using MCDMA Bypass Mode

This design example enables Avalon-MM PIO master which bypasses the DMA path. The Avalon-MM PIO master allows application to perform single, non-bursting register read/write operation with on-chip memory.

This design example only supports PIO functionality and does not perform DMA operations. Hence, the Avalon-ST DMA ports are not connected.

The design example includes the Multi Channel DMA for PCI Express IP Core with the parameters you specified and following components:
  • resetIP – Reset Release IP that holds the Multi Channel DMA in reset until the entire FPGA fabric enters user mode.
  • MEM_PIO – On-chip memory for the PIO operation. Connected to the MCDMA Avalon-MM PIO Master (rx_pio_master) port that is mapped to PCIe BAR2.
Transfer mode option supported in test application software (perfq_app) command line:
  • PIO test: -o

For a description of which driver(s) to use with this design example, refer to Driver Support.

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