Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

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ID 683517
Date 4/29/2022
Public
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2.3.2.1. Simulation Results

Note: The simulation and hardware test results were generated with MCDMA H-Tile.

Testbench writes 4 KB of incrementing pattern to on-chip memory and read back via Avalon-MM PIO interface. This design example testbench doesn’t simulate H2D/D2H data movers.

Figure 7. Simulation Log
Figure 8. Simulation Waveform

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