Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide
ID
683517
Date
4/29/2022
Public
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3.5.2.6.1. Build and Install Netdev Driver
3.5.2.6.2. Enable VFs if SRIOV is Supported
3.5.2.6.3. Configure the Number of Channels Supported on the Device
3.5.2.6.4. Configure the MTU Value
3.5.2.6.5. Configure the Device Communication
3.5.2.6.6. Configure Transmit Queue Selection Mechanism
3.5.2.6.7. Test Procedure by Using Name Space Environment
3.5.2.6.8. PIO Test
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2.3.2.1. Simulation Results
Note: The simulation and hardware test results were generated with MCDMA H-Tile.
Testbench writes 4 KB of incrementing pattern to on-chip memory and read back via Avalon-MM PIO interface. This design example testbench doesn’t simulate H2D/D2H data movers.
Figure 7. Simulation Log

Figure 8. Simulation Waveform
