Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/29/2022
Public

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Document Table of Contents

2.1.3. MCDMA F-Tile Design Examples for Endpoint

Table 5.  MCDMA F-Tile Design Examples for Endpoint
Design Example MCDMA Settings
User Mode Interface Type
AVMM DMA

Multi-Channel DMA

BAM + MCDMA

AVMM
Device-side Packet Loopback

Multi-Channel DMA

AVST 4 Ports
AVST 1 Port
Packet Generate/Check

Multi-Channel DMA

AVST 4 Ports
AVST 1 Port
PIO using MQDMA Bypass Mode

Multi-Channel DMA

BAM + MCDMA

AVMM

AVST 4 Ports

AVST 1 Port

Bursting Master n/a
BAM + BAS n/a
Data Mover Only n/a
Traffic Generator/Checker BAM + BAS n/a
External Descriptor Controller Data Mover Only n/a
Note:
  1. Hardware support is planned in future release.
  2. MCDMA F-Tile design example doesn’t support multiple physical functions and SR-IOV for simulation.

For information about supported simulators, refer to Supported Simulators.

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