Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

Download
ID 683517
Date 4/29/2022
Public
Document Table of Contents
Document Table of Contents
1. Introduction 2. Design Example Detailed Description 3. Design Example Quick Start Guide 4. User Guide Archives 5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide
1. Introduction
1.1. Terms and Acronyms 1.2. MCDMA IP Modes
2. Design Example Detailed Description
2.1. Design Example Overview 2.2. Hardware and Software Requirements 2.3. PIO Using MCDMA Bypass Mode 2.4. Avalon-ST Packet Generate/Check 2.5. Avalon-ST Device-side Packet Loopback 2.6. Avalon-MM DMA 2.7. BAM_BAS Traffic Generator and Checker 2.8. External Descriptor Controller
2.1. Design Example Overview
2.1.1. MCDMA H-Tile Design Examples for Endpoint 2.1.2. MCDMA P-Tile Design Examples for Endpoint 2.1.3. MCDMA F-Tile Design Examples for Endpoint
2.3. PIO Using MCDMA Bypass Mode
2.3.1. Avalon-ST PIO Using MCDMA Bypass Mode 2.3.2. Avalon-MM PIO Using MCDMA Bypass mode
2.3.1. Avalon-ST PIO Using MCDMA Bypass Mode
2.3.1.1. Four-Port Avalon-ST PIO Using MCDMA Bypass Mode 2.3.1.2. Single-Port Avalon-ST PIO Using MCDMA Bypass Mode
2.3.1.1. Four-Port Avalon-ST PIO Using MCDMA Bypass Mode
2.3.1.1.1. Simulation Result 2.3.1.1.2. Hardware Test Result
2.3.2. Avalon-MM PIO Using MCDMA Bypass mode
2.3.2.1. Simulation Results 2.3.2.2. Hardware Test Results
2.4. Avalon-ST Packet Generate/Check
2.4.1. Four-Port Avalon-ST Packet Generate/Check 2.4.2. Single-Port Avalon-ST Packet Generate/Check
2.4.1. Four-Port Avalon-ST Packet Generate/Check
2.4.1.1. Simulation Results 2.4.1.2. Hardware Test Results
2.4.2. Single-Port Avalon-ST Packet Generate/Check
2.4.2.1. Simulation Waveforms 2.4.2.2. Simulation Log
2.5. Avalon-ST Device-side Packet Loopback
2.5.1. Simulation Results 2.5.2. Hardware Test Results
2.6. Avalon-MM DMA
2.6.1. Simulation Results 2.6.2. Hardware Test Results
2.7. BAM_BAS Traffic Generator and Checker
2.7.1. BAM_BAS Traffic Generator and Checker Example Design Register Map
2.8. External Descriptor Controller
2.8.1. Registers 2.8.2. Hardware Test Results
2.8.1. Registers
2.8.1.1. GCSR Registers (Base address 64’h00000) 2.8.1.2. QCSR Registers(Base address 64’h10000)
3. Design Example Quick Start Guide
3.1. Design Example Directory Structure 3.2. Generating the Example Design using Intel® Quartus® Prime 3.3. Simulating the Design Example 3.4. Compiling the Example Design in Intel® Quartus® Prime 3.5. Running the Design Example Application on a Hardware Setup
3.2. Generating the Example Design using Intel® Quartus® Prime
3.2.1. Procedure
3.3. Simulating the Design Example
3.3.1. Testbench Overview 3.3.2. Supported Simulators 3.3.3. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example 3.3.4. Run the Simulation Script 3.3.5. View the Results
3.5. Running the Design Example Application on a Hardware Setup
3.5.1. Program the FPGA 3.5.2. Quick Start Guide
3.5.2. Quick Start Guide
3.5.2.1. Software Test Setup 3.5.2.2. Driver Support 3.5.2.3. MCDMA Custom Driver 3.5.2.4. MCDMA DPDK Poll Mode Driver 3.5.2.5. MCDMA Kernel Mode Character Device Driver 3.5.2.6. MCDMA Kernel Mode Network Device Driver
3.5.2.3. MCDMA Custom Driver
3.5.2.3.1. Prerequisites 3.5.2.3.2. Software Setup 3.5.2.3.3. Run the Reference Example Application 3.5.2.3.4. Testing Bitstream Configuration beyond 256 Channels 3.5.2.3.5. External Descriptor Mode Verification
3.5.2.4. MCDMA DPDK Poll Mode Driver
3.5.2.4.1. Prerequisites 3.5.2.4.2. Install PMD and Test Application 3.5.2.4.3. Run the Reference Example Application
3.5.2.5. MCDMA Kernel Mode Character Device Driver
3.5.2.5.1. Prerequisites 3.5.2.5.2. Software Setup 3.5.2.5.3. Examples
3.5.2.6. MCDMA Kernel Mode Network Device Driver
3.5.2.6.1. Build and Install Netdev Driver 3.5.2.6.2. Enable VFs if SRIOV is Supported 3.5.2.6.3. Configure the Number of Channels Supported on the Device 3.5.2.6.4. Configure the MTU Value 3.5.2.6.5. Configure the Device Communication 3.5.2.6.6. Configure Transmit Queue Selection Mechanism 3.5.2.6.7. Test Procedure by Using Name Space Environment 3.5.2.6.8. PIO Test
1. Introduction
2. Design Example Detailed Description
3. Design Example Quick Start Guide
4. User Guide Archives
5. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide

1.2. MCDMA IP Modes

The following table summarizes the MCDMA IP variants, IP mode and FPGA Development Kit board supported for design example hardware test.

Table 2.  MCDMA IP Modes and FPGA Development Kit for Design Examples
MCDMA IP IP Mode FPGA Development Kit Board for Design Example Hardware Test
PCI Express Application Data Width Application Clock Frequency
MCDMA H-Tile Gen3 x16 512 bits 250 MHz

Intel Stratix 10 GX H-Tile Production FPGA Development Kit

Intel Stratix 10 MX H-Tile Production FPGA Development Kit
Gen3 x8 256 bits 250 MHz
MCDMA P-Tile Gen4x16 512 bits

Stratix 10 DX: 400/350 MHz

Agilex: 500/450/400/350 MHz

Intel Stratix 10 DX P-Tile Production FPGA Development Kit

Intel Agilex F-Series P-Tile ES0 FPGA Development Kit
Gen4 x8* 256 bits

Stratix 10 DX: 400/350 MHz

Agilex: 500/450/400/350 MHz
Gen3 x16 512 bits 250 MHz
Gen3 x8* 256 bits 250 MHz
MCDMA F-Tile Gen4 1x16 512 bits 500/400/350 MHz None
Note: MCDMA F-Tile Hardware support may be added in a future release.
Gen4 1x8* 256 bits 500/400/350 MHz
Gen3 1x16 512 bits 250 MHz
Gen3 1x8* 256 bits 250 MHz
Note: * = MCDMA supports single x8 mode only. Bifurcated x8x8 mode is not supported.
Note: Hardware design examples are supported for MCDMA H-Tile and P-Tile only.

For more information about MCDMA IP, refer to the Multi Channel DMA Intel FPGA IP for PCI Express User Guide.

Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message