Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

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ID 683517
Date 4/29/2022
Public
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1.2. MCDMA IP Modes

The following table summarizes the MCDMA IP variants, IP mode and FPGA Development Kit board supported for design example hardware test.

Table 2.  MCDMA IP Modes and FPGA Development Kit for Design Examples
MCDMA IP IP Mode FPGA Development Kit Board for Design Example Hardware Test
PCI Express Application Data Width Application Clock Frequency
MCDMA H-Tile Gen3 x16 512 bits 250 MHz

Intel Stratix 10 GX H-Tile Production FPGA Development Kit

Intel Stratix 10 MX H-Tile Production FPGA Development Kit

Gen3 x8 256 bits 250 MHz
MCDMA P-Tile Gen4x16 512 bits

Stratix 10 DX: 400/350 MHz

Agilex: 500/450/400/350 MHz

Intel Stratix 10 DX P-Tile Production FPGA Development Kit

Intel Agilex F-Series P-Tile ES0 FPGA Development Kit

Gen4 x8* 256 bits

Stratix 10 DX: 400/350 MHz

Agilex: 500/450/400/350 MHz

Gen3 x16 512 bits 250 MHz
Gen3 x8* 256 bits 250 MHz
MCDMA F-Tile Gen4 1x16 512 bits 500/400/350 MHz None
Note: MCDMA F-Tile Hardware support may be added in a future release.
Gen4 1x8* 256 bits 500/400/350 MHz
Gen3 1x16 512 bits 250 MHz
Gen3 1x8* 256 bits 250 MHz
Note: * = MCDMA supports single x8 mode only. Bifurcated x8x8 mode is not supported.
Note: Hardware design examples are supported for MCDMA H-Tile and P-Tile only.

For more information about MCDMA IP, refer to the Multi Channel DMA Intel FPGA IP for PCI Express User Guide.

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