2.4.1. Four-Port Avalon-ST Packet Generate/Check
This design example performs H2D and D2H multi channel DMA via Avalon-ST streaming as well as PIO operations. The Multi Channel DMA for PCI Express IP core provides four independent Avalon-ST Source/Sink ports. DMA channel and Avalon-ST port has 1:1 mapping.
This design example instantiates a packet generator and checker module.
For H2D (Tx) DMA, the host populates the descriptor rings, allocates Tx packet buffers in the host memory, and fills the Tx buffers with a predefined pattern. When the application updates the Queue Tail Pointer register (Q_TAIL_POINTER), the MCDMA IP starts the H2D DMA and sends the received data to the packet checker module, which verifies the data integrity.
For D2H (Rx) DMA, packets generated from a packet generator module are transferred to the host memory, where the host checks the data integrity.
For Bidirectional DMA, the packet generator and checker modules transmit/receive the packets simultaneously.
In addition, the design example enables Avalon-MM PIO master which bypasses the DMA path. It allows application to perform single, non-bursting register read/write operation with on-chip memory block. Also, test application software, perfq_app, uses the Avalon-MM PIO Master port to configure the Packet Generator and Checker.
- resetIP – Reset Release IP that holds the Multi Channel DMA in reset until the entire FPGA fabric enters user mode.
- MEM_PIO – On-chip memory for the PIO operation. Connected to the MCDMA Avalon-MM PIO Master (rx_pio_master) port that is mapped to PCIe BAR2.
- GEN_CHK – Packet Generator and Checker for MCDMA. Connected to the MCDMA Avalon-ST Source (h2d_st_x) and Avalon-ST Sink (d2h_st_x) ports.
- PIO test: -o
- DMA test: -t (Tx), -r (Rx), -z (Bidirectional)
For a description of which driver(s) to use with this design example, refer to Driver Support.