Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/29/2022
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Document Table of Contents

3.1. Design Example Directory Structure

Table 32.  Directory Structure
Directory / File Sub-directory / File Sub-directory / File Sub-directory / File Sub-directory / File Note
pcie_ed sim pcie_ed.v Design example top-level HDL
<simulators> <simulation scripts> pcie_ed simulation directory
synth pcie_ed.v Design example top-level HDL

<Components automatically generated by Platform Designer>

 
pcie_ed_tb pcie_ed_tb sim pcie_ed_tb.v Testbench including Intel FPGA BFM
<simulators> <simulation script> Testbench simulation directory
ip pcie_ed_tb DUT_pcie_tb_ip   Intel FPGA BFM (RP)
pcie_ed_tb.qsys Testbench Platform Designer file
pcie_ed.ipx  
software dpdk dpdk drivers net  
examples mcdma-test  
patches v20.05-rc1  
Licenses license_bsd.txt    
version.txt      
kernel common      
driver kmod mcdma-custom-driver Kernel driver
mcdma-chardev-driver
mcdma-netdev-driver
Licenses license_bsd.txt    
user cli perfq_app <test application software> Test Application
README Readme file
sample ref.c Reference API flow
devmem    
simple_app    
testapp    
common include regs MCDMA and Pkt Gen/Chk registers
mk    
src    
libmqdma <user space library files> User space library
Licenses      
Readme     Readme file
readme Readme file
ip pcie_ed <Design example IP components>  
pcie_ed.qpf   Quartus project file
pcie_ed.qsf   Quartus setting file
pcie_ed.qsys   Design example Platform Designer file

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