Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide
ID
683517
Date
4/29/2022
Public
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3.5.2.6.1. Build and Install Netdev Driver
3.5.2.6.2. Enable VFs if SRIOV is Supported
3.5.2.6.3. Configure the Number of Channels Supported on the Device
3.5.2.6.4. Configure the MTU Value
3.5.2.6.5. Configure the Device Communication
3.5.2.6.6. Configure Transmit Queue Selection Mechanism
3.5.2.6.7. Test Procedure by Using Name Space Environment
3.5.2.6.8. PIO Test
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2.6.1. Simulation Results
No simulation for this Avalon-MM DMA design example is available in the current Intel® Quartus® Prime release.