Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/29/2022
Public

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2.6.2. Hardware Test Results

The Custom Driver was used to generate the following output:
Figure 30. PIO Test-o option
Note: The PIO test was run with MCDMA H-Tile.
Figure 31. H2D Avalon-MM Write-t option. Note: This hardware test was run with the Intel® Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
Note: Hardware test with P-Tile Gen4 x16 may be added in a future release.
Figure 32. H2D Avalon-MM Write with Data Validation Enabled-t -v option. Note: This hardware test was run with the Intel® Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
Note: Hardware test with P-Tile Gen4 x16 may be added in a future release.
Figure 33. D2H Avalon-MM Read-r option. Note: This hardware test was run with the Intel® Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
Note: Hardware test with P-Tile Gen4 x16 may be added in a future release.

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