Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/29/2022
Public

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3.5.2.2. Driver Support

The table below summarizes the driver support for the MCDMA design example variants. It uses the following acronyms:
  • User Space I/O (UIO): A kernel base module that the PCIe device uses to expose its resources to user space.
  • Virtual Function I/O (VFIO) driver: An IOMMU/device agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment.
  • Data Plane Development Kit (DPDK): Consists of libraries to accelerate packet processing workloads running on a wide variety of CPU architectures.
Table 37.  Driver Support for MCDMA Design Examples
Parameter Custom Driver DPDK Driver Kernel Mode Chardev Driver Kernel Mode Netdev Driver
Description Also known as the user mode driver, this driver is created to support both UIO and VFIO base kernelmodules. This driver provides custom APIs and can be used without depending on any framework. This DPDK Poll Mode Driver (PMD) uses the DPDK framework. The PMD will expose the device as an ethernet device. It supports both UIO and VFIO base kernel modules. Existing DPDK applications can be integrated with the MCDMA PMD. Kernel Mode Chardev Driver exposes the MCDMA IP through the char dev interface & using standard chardev file operations performs DMA transfers. Kernel Mode Netdev Driver exposes the MCDMA IP as a Network Device and enables standard applications to perform network data transfers using the Linux network stack.
Directory/Driver Path <example_design>/software/user <example_design>/software/dpdk <example design>/software/kernel/ <example design>/software/kernel/
SR-IOV Support Yes Yes No Yes
Multi channel DMA Avalon-MM DMA Design Example Yes, up to 2K Channels Yes, up to 2K Channels Yes, up to 2K Channels No
Multi channel DMA Avalon-MM DMA with SRIOV Design Example Yes, up to 2K Channels Yes, up to 2K Channels No No
BAM+MCDMA Avalon-MM DMA Design Example Yes, up to 2K Channels Yes, up to 2K Channels No No
BAM+MCDMA Avalon-MM DMA with SR-IOV Design Example Yes, up to 2K Channels Yes, up to 2K Channels No No
Multi channel DMA Avalon-MM PIO using MQDMA Bypass Mode Design Example Yes Yes Yes No
Multi channel DMA Avalon-ST 4-Port PIO using MQDMA Bypass Mode Design Example Yes Yes Yes No
Multi channel DMA Avalon-ST 1-port PIO using MQDMA Bypass Mode Design Example Yes Yes Yes No
BAM+MCDMA Avalon-MM PIO using MQDMA Bypass Mode Design Example Yes Yes No No
BAM+MCDMA Avalon-ST 4-Port PIO using MQDMA Bypass Mode Design Example Yes Yes No No
BAM+MCDMA Avalon-ST 1-Port PIO using MQDMA Bypass Mode Design Example Yes Yes No No
Bursting Master PIO using MQDMA Bypass Mode Design Example Yes Yes No No
Bursting Slave PIO using MQDMA Bypass Mode Design Example Yes Yes No No
BAM+BAS PIO using MQDMA Bypass Mode Design Example Yes Yes No No
Data Mover Only PIO using MQDMA Bypass Mode Design Example Yes No No No
Multi channel DMA Avalon 1-port Device-side Packet Loopback Design Example Yes Yes, 256 channels Yes, 256 channels Yes, support 4 PFs, 64 channel per PF
Multi channel DMA Avalon 1-port Device-side Packet Loopback with SRIOV Design Example Yes No No No
Multi channel DMA Avalon 4-port Device-side Packet Loopback Design Example Yes, 1 channel per port Yes, 1 channel per port Yes, 1 channel per port No
Multi channel DMA Avalon1-port Packet Generate/ Check Design Example Yes Yes, 256 channels Yes, 256 channels No
Multi channel DMA Avalon 1-port Packet Generate/ Check with SR-IOV Design Example Yes No No No
Multi channel DMA Avalon 4-port Packet Generate/ Check Design Example Yes, 1 channel per port Yes, 1 channel per port Yes, 1 channel per port No
BAM+BAS Traffic Generator/Checker Design Example Yes Yes No No
Data Mover Only External Descriptor Controller Design Example Yes No No No