Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

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ID 683517
Date 4/29/2022
Public
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2.8.1.2. QCSR Registers(Base address 64’h10000)

This space contains control and status registers for external descriptor controller. Host maintains separate descriptor ring for both D2H & H2D queues. External descriptor controller example design supports 16 channels. Descriptor context for each channel can be updates in the following CSR registers.

Address [11:8] = Channel number (Queue ID).

Address [7] = Data Mover direction. 0 = D2H, 1 = H2D.

Address [6:3] = Register offset.

Table 20.  D2H Start Address (Offset 8’h00)
Bit[63:0] Name R/W Default Description

[63:0]

Start_addr

R/W

0

D2H ring buffer start address [63:0].

Table 21.  D2H Buffer Size (Offset 8’h08)
Bit[63:0] Name R/W Default Description
[63:16] rsvd     Reserved

[15:0]

size

R/W

0

D2H ring buffer size

Table 22.  D2H Tail Pointer (Offset 8’h10)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

   

Reserved

[15:0]

tail_ptr

R/W

0

D2H ring buffer tail pointer, Updated by Host SW & Read-only for DMA HW.

Table 23.  D2H Head Pointer (Offset 8’h18)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

   

Reserved

[15:0]

head_ptr

RO

0

D2H ring buffer head pointer, Updated by DMA HW & Read-only for Host SW.

Table 24.  D2H Write back Address (Offset 8’h20)
Bit[63:0] Name R/W Default Description

[63:0]

wb_addr

R/W

0

D2H write back address [63:0].

Table 25.  D2H Completion Pointer (Offset 8’h28)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

   

Reserved

[15:0]

cmpl_ptr

RO

0

D2H ring buffer completion pointer, Updated by DMA HW & Read-only for Host SW.

Table 26.  H2D Start address (Offset 8’h80)
Bit[63:0] Name R/W Default Description

[63:0]

Start_addr

R/W

0

H2D ring buffer start address [63:0].

Table 27.  H2D Buffer Size (Offset 8’h88)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

   

Reserved

[15:0]

size

R/W

0

H2D ring buffer size

Table 28.  H2D Tail Pointer (Offset 8’h90)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

   

Reserved

[15:0]

tail_ptr

R/W

0

H2D ring buffer tail pointer, Updated by Host SW & Read-only for DMA HW.

Table 29.  H2D Head Pointer (Offset 8’h98)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

   

Reserved

[15:0]

head_ptr

RO

0

H2D ring buffer head pointer, Updated by DMA HW & Read-only for Host SW.

Table 30.  H2D Write back address (Offset 8’hA0)
Bit[63:0] Name R/W Default Description

[63:0]

wb_addr

R/W

0

H2D write back address [63:0].

Table 31.  H2D Completion Pointer (Offset 8’hA8)
Bit[63:0] Name R/W Default Description

[63:16]

rsvd

   

Reserved

[15:0]

cmpl_ptr

RO

0

H2D ring buffer completion pointer, Updated by DMA HW & Read-only for Host SW.

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