Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/29/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.1.1.1. Simulation Result

Note: The simulation and hardware test results were generated with MCDMA H-Tile.

Testbench writes 4 KB of incrementing pattern to on-chip memory and read back via Avalon-MM PIO interface. This design example testbench doesn’t simulate H2D/D2H data movers.

Figure 2. Simulation Log
Figure 3. Simulation Waveform

Did you find the information on this page useful?

Characters remaining:

Feedback Message