Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

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ID 683517
Date 4/29/2022
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3.3.2. Supported Simulators

The following tables show supported simulators for MCDMA example designs.
Note: Root Port mode simulation is supported by VCS simulator only.
Table 33.  Supported Simulators for MCDMA IP H-Tile
Tile Design Example User Mode VCS VCS MX Xcelium Questa* Questa*-Intel® FPGA Edition
H-Tile PIO using Bypass mode Multi channel DMA Bursting Master BAM+BAS BAM+MCDMA Yes(3) Yes(3) Yes(3) Yes(3) No
AVMM DMA Multi channel DMA BAM+MCDMA Yes(1) Yes(1) Yes(1) Yes(1) No
Device-side Packet Loopback Multi channel DMA Yes(2) Yes(2) Yes(2) Yes(2) No
Packet Generate/Check Multi channel DMA Yes(2) Yes(2) Yes(2) Yes(2) No
Traffic Generator/Checker BAM+BAS Yes(3) Yes(2) Yes(2) Yes(2) No
Note:
  1. Support SR-IOV up to 4 physical function for Multi channel DMA mode, 1 physical function for BAM+MCDMA and mode, refer to H-Tile Avalon Streaming Intel FPGA IP for PCI Express* User Guide for supported physical function or virtual function combinations.
  2. Support SR-IOV with 1 physical function for Multi channel DMA and BAM+MCDMA and user modes, refer to H-Tile Avalon Streaming Intel FPGA IP for PCI Express* User Guide for supported physical function or virtual function combinations.
  3. Support SR-IOV with 1 physical function, refer to H-Tile Avalon Streaming Intel FPGA IP for PCI Express* User Guide for supported physical function or virtual function combinations.
Table 34.  Supported Simulators for MCDMA IP P-Tile
Tile Design Example User Mode VCS VCS MX Xcelium Questa* Questa*-Intel® FPGA Edition
P-Tile PIO using Bypass mode Multi channel DMA Bursting Master BAM+BAS BAM+MCDMA Data Mover Only Yes Yes No Yes Yes
AVMM DMA Multi channel DMA BAM+MCDMA Yes Yes No No No
Device-side Packet Loopback Multi channel DMA Yes Yes No No No
Packet Generate/Check Multi channel DMA Yes Yes No No No
Traffic Generator/Checker BAM+BAS Yes Yes No No No
External Descriptor Controller Data Mover Only Yes Yes No No No
Note: SR-IOV is not supported in simulation
Table 35.  Supported Simulators for MCDMA IP F-Tile
Tile Design Example User Mode VCS VCS MX Xcelium Questa* Questa*-Intel® FPGA Edition
F-Tile PIO using Bypass mode Multi channel DMA Bursting Master BAM+BAS BAM+MCDMA Data Mover Only Yes Yes Yes Yes Yes
AVMM DMA Multi channel DMA BAM+MCDMA Yes Yes Yes Yes No
Device-side Packet Loopback Multi channel DMA Yes Yes Yes Yes No
Packet Generate/Check Multi channel DMA Yes Yes Yes Yes No
Traffic Generator/Checker BAM_BAS Yes Yes Yes Yes No
External Descriptor Controller Data Mover Only Yes Yes No No No
Note: SR-IOV is not supported in simulation

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