Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/29/2022

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Document Table of Contents Simulation Results

Note: The simulation result was generated with MCDMA H-Tile.
Note: For detailed description about the testbench for this design example, refer to Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example.
Figure 11. H2D Simulation Log
Figure 12. H2D Simulation Waveform
Figure 13. D2H Simulation Log
Figure 14. D2H Simulation Waveform