Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

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ID 683517
Date 4/29/2022
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3.3.3. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example

The DMA testbench for the Avalon-ST Packet Generate/Check design example demonstrates the following two major tasks:
  • Host-to-Device: Transferring packets stored in the host memory to the Packet Checker in the design example user logic, where a checker module verifies the integrity of the packet
  • Device-to-Host: Packets generated from a Generator module are transferred to the host memory where the host checks the packet integrity
Note: This testbench implements transfer of one packet with length of 4096 bytes.
The DMA testbench for the design example completes the following tasks for each of the 4 ports supported by the DUT:
  1. Set up 4096 bytes of incrementing data pattern for testing data movement from the host to the device and then back to the host.
  2. Write the expected packet length value (4096 bytes) to the Packet Generation and Checker in the design example user logic through the PIO. This value is used by the Packet checker module for testing packet integrity.
  3. MSI-X is enabled and configured for launching a memory write to signal the end of each descriptor’s DMA transaction. Write-Back function is kept disabled for the simulation.
  4. Set up the H2D (Host-to-Device) queue in the Multi Channel DMA.
  5. Set up three H2D descriptors in the host memory, with the source address pointing to the incrementing data pattern locations in the host memory. The start of packet (SOF) and end of packet (EOF) markers along with packet length are indicated in the descriptors.
  6. At the last step of the Queue programming, the Multi Channel DMA tail pointer register is written, which triggers the Multi Channel DMA to start the H2D DMA transaction.
  7. The previous step instructs the H2D Data Mover to fetch the descriptors from the host memory.
  8. The Multi Channel DMA H2D Data Mover reads the data from the host memory and forwards the packet to the Packet Generator and Checker through the AVST Streaming interface.
  9. The checker module receives the packet and checks for integrity by testing the data pattern, length as expected and proper receipt of the “end of packet” marker. If the packet is found to be proper, the good packet count is incremented by 1 else the bad packet count is incremented.
  10. The testbench does a PIO read access of the Good Packet Count and Bad Packet Count registers and displays the test success or failure status.
  11. MSI-X write commands are triggered for every description or completion which are checked by the testbench for proper receipt.
  12. Next, set up the D2H (Device-to-Host) Queue.
  13. Setup three D2H descriptors in the host memory, with the destination address pointing to a new address space in host memory which is pre-filled with all zeroes.
  14. At the last step of the Queue programming, the Multi Channel DMA tail pointer register is written, which triggers the Multi Channel DMA to start the D2H DMA transaction.
  15. The previous step instructs the H2D Data Mover to fetch the descriptors from the host memory to start the D2H DMA transaction.
  16. The Multi Channel DMA D2H Data Mover reads the incoming packet from the Packet Generator and writes the data to the host memory according to the descriptors fetched in the previous step.
  17. MSI-X write commands are triggered for every description completion which are checked by the testbench for proper receipt.
  18. Compares the data written back to the system memory in D2H task with the standard incrementing pattern and declare test success/failure.

The simulation reports Simulation stopped due to successful completion if no errors occur.

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