Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/29/2022
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Document Table of Contents

2.1.2. MCDMA P-Tile Design Examples for Endpoint

Table 4.  MCDMA P-Tile Design Examples for Endpoint
Design Example MCDMA Settings Driver Support
User Mode Interface Type
AVMM DMA

Multi-Channel DMA

BAM + MCDMA

AVMM

Custom

DPDK

Device-side Packet Loopback

Multi-Channel DMA

AVST 4 Ports

Custom

DPDK

AVST 1 Port

Custom

DPDK

Kernel Mode

Netdev

Packet Generate/Check

Multi-Channel DMA

AVST 4 Ports

Custom

DPDK

AVST 1 Port

Custom

DPDK

PIO using MQDMA Bypass Mode

Multi-Channel DMA

BAM + MCDMA

AVMM

AVST 4 Ports

AVST 1 Port

Custom

DPDK

Bursting Master n/a

Custom

DPDK

BAM + BAS n/a

Custom

DPDK

Data Mover Only n/a

Custom

DPDK

Traffic Generator/Checker BAM + BAS n/a

Custom

DPDK

External Descriptor Controller Data Mover Only n/a Custom
Note:
  1. MCDMA P-Tile design example doesn’t support multiple physical functions and SR-IOV for simulation.

For information about supported simulators, refer to Supported Simulators.

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