Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/29/2022
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2.1.1. MCDMA H-Tile Design Examples for Endpoint

Table 3.  MCDMA H-Tile Design Examples for Endpoint
Design Example MCDMA Settings Driver Support
User Mode Interface Type
AVMM DMA

Multi-Channel DMA

BAM + MCDMA

AVMM

Custom

DPDK

Device-side Packet Loopback

Multi-Channel DMA

AVST 4 Ports

Custom

DPDK

AVST 1 Port

Custom

DPDK

Kernel Mode

Netdev

Packet Generate/Check

Multi-Channel DMA

AVST 4 Ports

Custom

DPDK

AVST 1 Port

Custom

DPDK

PIO using MQDMA Bypass Mode

Multi-Channel DMA

BAM + MCDMA

AVMM

AVST 4 Ports

AVST 1 Port

Custom

DPDK

Bursting Master n/a

Custom

DPDK

BAM + BAS n/a

Custom

DPDK

Traffic Generator/Checker BAM + BAS n/a

Custom

DPDK

Note:
  1. MCDMA H-Tile design example supports SR-IOV with only 1 PF and its VFs for simulation in these configurations.
  2. Kernel mode driver doesn’t support SR-IOV.
  3. Netdev driver supports 4 PFs and 1 channel per PF.
  4. Packet Generate/Check and Device-side Packet loopback design example variants for BAM + MCDMA user mode of Avalon-ST interface type is temporary disabled

For information about supported simulators, refer to Supported Simulators.

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