18.104.22.168.1. Build and Install Netdev Driver 22.214.171.124.2. Enable VFs if SRIOV is Supported 126.96.36.199.3. Configure the Number of Channels Supported on the Device 188.8.131.52.4. Configure the MTU Value 184.108.40.206.5. Configure the Device Communication 220.127.116.11.6. Configure Transmit Queue Selection Mechanism 18.104.22.168.7. Test Procedure by Using Name Space Environment 22.214.171.124.8. PIO Test
- In the Intel® Quartus® Prime Pro Edition software, create a new project (File → New Project Wizard).
- Specify the Directory, Name, and Top-Level Entity.
- For Project Type, accept the default value, Empty project. Click Next.
- For Add Files click Next.
- For Family, Device & Board Settings, select Intel® Stratix® 10 (GX/SX/MX/TX/DX) or Intel® Agilex™ F-Series or Intel® Agilex™ I-Series and the Target Device for your design.
Note: The selected device is only used if you select None in Step 10c below.
- Click Finish.
- In the IP Catalog locate and add the Multi Channel DMA for PCI Express ( Intel® Stratix® 10 GX/MX devices), Multi Channel DMA P-Tile for PCI Express ( Intel® Stratix® 10 DX and Intel® Agilex™ devices), or Multi Channel DMA F-Tile for PCI Express* ( Intel® Agilex™ devices), which brings up the IP Parameter Editor.
- In the New IP Variant dialog box, specify a name for your IP. Click Create.
- On the IP Settings tabs, specify the parameters for your IP variation.
- On the Example Designs tab, make the following selections:
- For Example Design Files, turn on the Simulation and Synthesis options. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the example design generation time.
- For Generated HDL Format, only Verilog is available in the current release.
- For Target Development Kit, select the appropriate option.
Note: If you select None, the generated design example targets the device specified. Otherwise, the design example uses the device on the selected development board. If you intend to test the design in hardware, make the appropriate pin assignments in the .qsf file.Note: No Development Kit is supported for F-Tile in Intel® Quartus® Prime software version 21.3.
- For Currently Selected Example Design, select a design example from a pulldown menu. Available design examples depends on the User Mode and Interface type setting in MCDMA Settings under IP Settings tab. Available design examples for the Multi Channel DMA mode and Avalon-ST Interface type:
- PIO using MQDMA Bypass Mode
- Packet Generate/Check
- Device-side Packet Loopback
- PIO using MQDMA Bypass Mode
- AVMM DMA
- Select Generate Example Design to create a design example that you can simulate and download to hardware. If you target one of the Intel FPGA development kits, the device on that board supersedes the device previously selected in the Intel® Quartus® Prime Pro Edition project if the devices are different. When the prompt asks you to specify the directory for your example design, you can choose to accept the default directory ./intel_pcie_mcdma_0_example_design or choose another directory.
- Click Close on Generate Example Design Completed message.
- Close the IP Parameter Editor. Click File → Exit. When prompted with Save changes?, you do not need to save the .ip. Click Don’t Save.
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