Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

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ID 683517
Date 4/29/2022
Public
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3.3.4. Run the Simulation Script

Figure 41. Simulation Script
  1. Change to the testbench simulation directory, pcie_ed_tb/pcie_ed_tb/sim/<simulators> .
  2. Run the simulation script for the simulator of your choice. Refer to the table below.
  3. Analyze the results.
Table 36.  Steps to run the simulation
Simulator Simulation Directory Instructions

Questa* / Questa*-Intel® FPGA Edition

<example_design>/pcie_ed_tb/ pcie_ed _tb/sim/mentor/

  1. Invoke vsim (by typing vsim, which brings up a console window where you can run the following commands).
  2. do msim_setup.tcl
    Note: Alternatively, instead of doing Steps 1 and 2, you can type: vsim -c -do msim_setup.tcl
  3. ld_debug
  4. run -all
  5. A successful simulation ends with the following message: "Simulation stopped due to successful completion!"
VCS/VCSMX

<example_design> /pcie_ed_tb/ pcie_ed _tb/sim/synopsys/vcs

<example_design>/pcie_ed_tb/pcie_ed _tb/sim/synopsys/vcsmx

  1. sh vcs_setup.sh 
    USER_DEFINED_COMPILE_OPTIONS="" 
    USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final\ +vcs+vcdpluson\ -debug_all" 
    USER_DEFINED_SIM_OPTIONS="" 
  2. A successful simulation ends with the following message: "Simulation stopped due to successful completion!"
Xcelium

<example_design>/pcie_ed_tb/pcie_ed_tb/sim/xcelium

  1. sh xcelium_setup.sh 
    USER_DEFINED_SIM_OPTIONS="" 
    USER_DEFINED_ELAB_OPTIONS ="-timescale\ 1ns/1ps\ -NOWARN\ CSINFI"
  2. A successful simulation ends with the following message: "Simulation stopped due to successful completion!"
Note: Xcelium currently support for H-Tile only

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