12.2. Monolithic Transceivers in Intel® Agilex™ D-Series FPGAs and SoCs
The monolithic transceivers in Intel® Agilex™ D-Series FPGAs and SoCs enable low latencies for midrange FPGA applications. For long reach backplane-driving applications, the devices use advanced adaptive equalization circuits to equalize system loss.
All Intel® Agilex™ D-Series transceiver channels are equipped with these blocks:
- Dedicated PMA—provides primary interfacing capabilities to physical channels.
- Hardened PCS—supports 64b/66b encoding and decoding functions, data scrambling, block alignment, and gearboxing functions.
- FEC—Firecode FEC for 10/25 GbE BASE-KR/CR applications and Reed Solomon FEC.
A single PMA–PCS channel with independent clock domains forms each transceiver channel. Using a highly configurable clock distribution network, you can configure various bonded and non-bonded data rate within each transceiver bank.
28.1 Gbps NRZ
(1–28.1 Gbps continuous)
10/25 GbE FEC direct mode
(IEEE 802.3 Clause 74 Firecode FEC and Clause 91 RS-FEC hard IPs)
10/25 GbE PCS direct mode 47
(64b/66b hard IP)
|Independent transmitter and receiver to support combining simplex protocols|
PMA direct mode (bypass Ethernet and PCIe* hard IPs)
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