Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

12.2. Monolithic Transceivers in Intel® Agilex™ D-Series FPGAs and SoCs

The Intel® Agilex™ D-Series FPGAs and SoCs are equipped with NRZ transceivers optimized for a wide variety of applications, ranging from 1 Gbps to 28.1 Gbps NRZ.

The monolithic transceivers in Intel® Agilex™ D-Series FPGAs and SoCs enable low latencies for midrange FPGA applications. For long reach backplane-driving applications, the devices use advanced adaptive equalization circuits to equalize system loss.

All Intel® Agilex™ D-Series transceiver channels are equipped with these blocks:

  • Dedicated PMA—provides primary interfacing capabilities to physical channels.
  • Hardened PCS—supports 64b/66b encoding and decoding functions, data scrambling, block alignment, and gearboxing functions.
  • FEC—Firecode FEC for 10/25 GbE BASE-KR/CR applications and Reed Solomon FEC.

A single PMA–PCS channel with independent clock domains forms each transceiver channel. Using a highly configurable clock distribution network, you can configure various bonded and non-bonded data rate within each transceiver bank.

Table 37.  Transceiver Capabilities of Intel® Agilex™ FPGAs and SoCs
Capability Maximum Specification
Maximum speed

28.1 Gbps NRZ

(1–28.1 Gbps continuous)

FEC

10/25 GbE FEC direct mode

(IEEE 802.3 Clause 74 Firecode FEC and Clause 91 RS-FEC hard IPs)

PCS

10/25 GbE PCS direct mode 47

(64b/66b hard IP)

PCIe*
  • PCIe* 4.0 ×8 controller hard IP
  • PCIe* 4.0 ×4 controller hard IP

Transmitter/Receiver

Independent transmitter and receiver to support combining simplex protocols
PMA

PMA direct mode (bypass Ethernet and PCIe* hard IPs)

47 The PCS direct mode is supported on GbE and other protocols.

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