Intel® Agilex™ 7 FPGAs and SoCs Device Overview

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ID 683458
Date 1/10/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs 2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ 7 FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ 7 FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ 7 FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ 7 FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ 7 FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ 7 FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ 7 SoCs 12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ 7 FPGAs and SoCs M-Series 14. High-Performance Crypto Blocks in Intel® Agilex™ 7 FPGAs and SoCs F-Series and I-Series 15. Configuration via Protocol Using PCIe* for Intel® Agilex™ 7 FPGAs and SoCs 16. Device Configuration and the SDM in Intel® Agilex™ 7 FPGAs and SoCs 17. Partial and Dynamic Configuration of Intel® Agilex™ 7 FPGAs and SoCs 18. Device Security for Intel® Agilex™ 7 FPGAs and SoCs 19. SEU Error Detection and Correction in Intel® Agilex™ 7 FPGAs and SoCs 20. Power Management for Intel® Agilex™ 7 FPGAs and SoCs 21. Intel® Software and Tools for Intel® Agilex™ 7 FPGAs and SoCs 22. Revision History for the Intel® Agilex™ 7 FPGAs and SoCs Device Overview
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs x
1.1. Key Features and Innovations in Intel® Agilex™ 7 FPGAs and SoCs 1.2. Intel® Agilex™ 7 FPGAs and SoCs Block Diagram 1.3. Intel® Agilex™ 7 FPGAs and SoCs Summary of Features 1.4. Additional Features for Intel® Agilex™ 7 SoCs
2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan x
2.1. Intel® Agilex™ 7 FPGAs and SoCs F-Series 2.2. Intel® Agilex™ 7 FPGAs and SoCs I-Series 2.3. Intel® Agilex™ 7 FPGAs and SoCs M-Series 2.4. Available Options
10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs x
12.1. E-Tile Transceivers 12.2. P-Tile Transceivers 12.3. F-Tile Transceivers 12.4. R-Tile Transceivers
12.1. E-Tile Transceivers x
12.1.1. PMA Features in E-Tile Transceivers 12.1.2. PCS Features in E-Tile Transceivers
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs
2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Intel® Hyperflex™ Core Architecture
4. Adaptive Logic Module in Intel® Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Intel® Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Intel® Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Intel® Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Intel® Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Intel® Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Intel® Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Intel® Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Intel® Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Intel® Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Intel® Agilex™ 7 FPGAs and SoCs
18. Device Security for Intel® Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Intel® Agilex™ 7 FPGAs and SoCs
20. Power Management for Intel® Agilex™ 7 FPGAs and SoCs
21. Intel® Software and Tools for Intel® Agilex™ 7 FPGAs and SoCs
22. Revision History for the Intel® Agilex™ 7 FPGAs and SoCs Device Overview

12.3. F-Tile Transceivers

The F-Tile transceivers are general purpose transceivers.

Features of the F-Tile transceivers:

  • Speed options:
    • Four channels of 116 Gbps PAM4 or 58 Gbps NRZ
    • 12 channels of 58 Gbps PAM4 or 16 channels of 32 Gbps NRZ
  • Hard IP support for Ethernet and PCIe*
  • Other protocols support:
    • Multiprotocol support for CEI, Ethernet, CPRI, FlexE, 300 Gbps Interlaken, fibre channel, SR-IOV, SerialLite IV, OTN, JESD204B, JESD204C, FlexO, IEEE1588, GPON, SDI, Vby1, HDMI, and Display Port
    • PCIe* 4.0 ×16 support with P-Tile feature set, Precise Time Management, and PMA Direct mode
    • Configuration via protocol (CvP)
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