Intel® Agilex™ 7 FPGAs and SoCs Device Overview

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ID 683458
Date 2/20/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs 2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ 7 FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ 7 FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ 7 FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ 7 FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ 7 FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ 7 FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ 7 SoCs 12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ 7 FPGAs and SoCs M-Series 14. High-Performance Crypto Blocks in Intel® Agilex™ 7 FPGAs and SoCs F-Series and I-Series 15. Configuration via Protocol Using PCIe* for Intel® Agilex™ 7 FPGAs and SoCs 16. Device Configuration and the SDM in Intel® Agilex™ 7 FPGAs and SoCs 17. Partial and Dynamic Configuration of Intel® Agilex™ 7 FPGAs and SoCs 18. Device Security for Intel® Agilex™ 7 FPGAs and SoCs 19. SEU Error Detection and Correction in Intel® Agilex™ 7 FPGAs and SoCs 20. Power Management for Intel® Agilex™ 7 FPGAs and SoCs 21. Intel® Software and Tools for Intel® Agilex™ 7 FPGAs and SoCs 22. Revision History for the Intel® Agilex™ 7 FPGAs and SoCs Device Overview
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs x
1.1. Key Features and Innovations in Intel® Agilex™ 7 FPGAs and SoCs 1.2. Intel® Agilex™ 7 FPGAs and SoCs Block Diagram 1.3. Intel® Agilex™ 7 FPGAs and SoCs Summary of Features 1.4. Additional Features for Intel® Agilex™ 7 SoCs
2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan x
2.1. Intel® Agilex™ 7 FPGAs and SoCs F-Series 2.2. Intel® Agilex™ 7 FPGAs and SoCs I-Series 2.3. Intel® Agilex™ 7 FPGAs and SoCs M-Series 2.4. Available Options
10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs x
12.1. E-Tile Transceivers 12.2. P-Tile Transceivers 12.3. F-Tile Transceivers 12.4. R-Tile Transceivers
12.1. E-Tile Transceivers x
12.1.1. PMA Features in E-Tile Transceivers 12.1.2. PCS Features in E-Tile Transceivers
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs
2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Intel® Hyperflex™ Core Architecture
4. Adaptive Logic Module in Intel® Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Intel® Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Intel® Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Intel® Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Intel® Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Intel® Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Intel® Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Intel® Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Intel® Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Intel® Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Intel® Agilex™ 7 FPGAs and SoCs
18. Device Security for Intel® Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Intel® Agilex™ 7 FPGAs and SoCs
20. Power Management for Intel® Agilex™ 7 FPGAs and SoCs
21. Intel® Software and Tools for Intel® Agilex™ 7 FPGAs and SoCs
22. Revision History for the Intel® Agilex™ 7 FPGAs and SoCs Device Overview

2.3. Intel® Agilex™ 7 FPGAs and SoCs M-Series

Table 13.  M-Series FPGA Family Plan—Core FeaturesThe values in this table are maximum resources or performance.
Device Logic Element Adaptive Logic Module M20K MLAB HBM2E DRAM (GB) DSP Crypto Block
Count Size (Mb) Count Size (Mb) Count 18x19 Multiplier
AGM 032 3,245,000 1,100,000 15,932 311 55,000 33 16 / 32 9,375 18,750 —
AGM 039 3,851,520 1,305,600 18,960 370 65,280 40 16 / 32 12,300 24,600 —
Table 14.  M-Series FPGA Family Plan—Transceivers and HPSThe values in this table are maximum resources or performance.
Device

CXL* Lane

F-Tile R-Tile

HPS
Transceiver Channel

Ethernet Block

21

PCIe* Controller

22

PCIe* 23/

CXL* 24 Controller

FGT 25 FHT 26
32 Gbps

NRZ

 58 Gbps

PAM4

 58 Gbps

NRZ

 116 Gbps

PAM4
AGM 032 1627

64

 48

8

 8 4 28 4 29 1 Yes
AGM 039 1627

64

 48

8

 8 4 28 4 29 1 Yes
Table 15.  M-Series FPGA Package with F-TileTable reading example: In package 3184B of AGM 032, there are 720 GPIOs, of which, 360 are LVDS. There are four F-Tiles with FGT channels supporting a maximum total of 64× 32 Gbps NRZ or 48× 58 Gbps PAM4, and FHT channels supporting a maximum total of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4.
Device Package

(Grid Array: Hexagonal)
3184B

(56 mm × 45 mm)

0.92 mm pitch
GPIO LVDS F-Tile ×4
FGT FHT

32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4
AGM 032 720 360 64 48 8 8
AGM 039 720 360 64 48 8 8
Table 16.  M-Series FPGA Package with F-Tile and R-TileTable reading example: In package 3687A of AGM 032, there are 768 GPIOs, of which, 384 are LVDS. There are three F-Tiles with FGT channels supporting a maximum of 48× 32 Gbps NRZ or 36× 58 Gbps PAM4, and FHT channels supporting a maximum of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4. There is one R-Tile supporting a maximum of 16× PCIe* at up to 32 Gbps per lane, or 16× CXL* lanes.
Device Package

(Grid Array: Hexagonal)
3687A

(56 mm × 52.5 mm)

0.92 mm pitch

GPIO LVDS F-Tile ×3 R-Tile ×1
FGT FHT

32 Gbps

PCIe*

CXL*

32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4
AGM 032 768 384 48 36 8 8 16 16
AGM 039 768 384 48 36 8 8 16 16
Table 17.  M-Series FPGA Package with F-Tile and HBM2ETable reading example: In package 4700B of AGM 032, there are 768 GPIOs, of which, 384 are LVDS. There are three F-Tiles with FGT channels supporting a maximum total of 64× 32 Gbps NRZ or 48× 58 Gbps PAM4, and FHT channels supporting a maximum total of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4. The devices are available with 16 GB or 32 GB in-package HBM2E memory.
Device Package

(Grid Array: Hexagonal)
4700B

(56 mm × 66 mm)

0.92 mm pitch
GPIO LVDS F-Tile ×3 HBM2E (GB)
FGT FHT

32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4
AGM 032 768 384 64 48 8 8 16 / 32
AGM 039 768 384 64 48 8 8 16 / 32
Table 18.  M-Series FPGA Package with F-Tile, R-Tile, and HBM2ETable reading example: In package 4700A of AGM 032, there are 768 GPIOs, of which, 384 are LVDS. There are three F-Tiles with FGT channels supporting a maximum of 48× 32 Gbps NRZ or 36× 58 Gbps PAM4, and FHT channels supporting a maximum of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4. There is one R-Tile supporting a maximum of 16× PCIe* at up to 32 Gbps per lane. The devices are available with 16 GB or 32 GB in-package HBM2E memory.
Device Package

(Grid Array: Hexagonal)
4700A

(56 mm × 66 mm)

0.92 mm pitch
GPIO LVDS F-Tile ×3 R-Tile ×1 HBM2E (GB)
FGT FHT

32 Gbps

PCIe*

CXL*

32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4
AGM 032 768 384 48 36 8 8 16 16 16 / 32
AGM 039 768 384 48 36 8 8 16 16 16 / 32
Related Information
21 Maximum 10, 25, 40, 50, 100, 200, or 400 GbE MAC and FEC hard IP blocks.
22 Maximum PCIe* hard IP blocks ( PCIe* 4.0 ×16) or bifurcatable two PCIe* 4.0 ×8 (EP) or four PCIe* 4.0 ×4 (RP).
23 Maximum PCIe* hard IP blocks ( PCIe* 5.0 ×16) or bifurcatable two PCIe* 5.0 ×8 (EP) or four PCIe* 5.0 ×4 (RP).
24 Maximum CXL* hard IP blocks ( PCIe* 5.0 ×16) endpoint.
25 Maximum F-Tile general purpose transceiver (FGT) RS and KP FEC NRZ up to 32 Gbps, or PAM4 up to 58 Gbps.
26 Maximum F-Tile high speed transceiver (FHT) RS and KP FEC NRZ up to 58 Gbps, or PAM4 up to 116 Gbps.
27 Available in package 3687A.
28 Maximum of four F-Tiles in package 3184B.
29 Maximum of four PCIe* controllers in package 3184B.
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