17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs
The embedded PCIe* hard IP operates in autonomous mode before the FPGA is configured. Using this hard IP, you can power up and activate the PCIe* bus within the 100 ms time allowed by the PCIe* specification.
The Intel® Agilex™ FPGAs and SoCs also support partial reconfiguration across the PCIe* bus. This capability reduces system downtime by keeping the PCIe* link active during device reconfiguration.
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